Liquid crystal driver and liquid crystal display device using the same

ABSTRACT

A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.

CROSS-REFERENCE TO RELATED APPLICATION

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,774,106. The reissue applications are applicationSer. No. 09/324,168, now U.S. Pat. No. RE39,366; Ser. Nos. 11/406,488;11/980,700; 11/980,691; and the present application: all of which arereissues of U.S. Pat. No. 5,774,106.

This application is related to application Ser. No. 08/135,357 filed onOct. 19, 1993, entitled “Liquid Crystal Display Driving Method/DrivingCircuit Capable of Being Driven with Equal Voltages” which is assignedto the same assignee as the present application. The contents ofapplication Ser. No. 08/135,537 are incorporated herein by reference.This application is a continuation reissue of application of U.S.reissue application No. 11/406,488, filed April 19, 2006 now U.S. Pat.No. Re. 40,973, which is a continuation reissue application of U.S.reissue application Ser. No. 09/324,168, filed Jun. 2, 1999, now U.S.Reissue Pat. RE 39,366, which is a reissue application of U.S. Pat. No.5,774,106, issued Jun. 30, 1998, the subject matter of which isincorporated by reference herein. This application is related tocontinuation reissue U.S. application Ser. No. 11/980,691, filed Oct.31, 2007, and continuation reissue U.S. application Ser. No. 11/980,700,filed Oct. 31, 2007, which are continuation reissues of continuationreissue U.S. application Ser. No. 11/406,488, filed Apr. 19, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal driver and a liquidcrystal display device using the same and, particularly, relates to anactive matrix type liquid crystal driver and a liquid crystal displaydevice using the same.

2. Description of the Related Art

A conventional liquid crystal driver using a data driver LSI HD66310described in Hitachi LCD driver LSI databook (Published by Hitachi Ltd.,March 1994, pp. 1166-1185) will be explained below.

FIG. 2 is a configuration diagram of the conventional data driverHD66310.

In FIG. 2, the reference numeral 201 designates a data driver; 202,display data transferred from a system thereto; 203, a group of controlsignals for controlling the data driver; 204, a timing control circuit;205, a control signal for controlling the timing of latching the displaydata 202; 206, display data; 207, a display timing signal; 208, a latchaddress control circuit; 209, a group of latch signals generated by thelatch address control circuit 208; 210, a latch circuit for latching thedisplay data 206 successively; 211, display data latched by the latchcircuit 210 simultaneously; 212, a latch circuit for latching thedisplay data 211 simultaneously on the basis of the timing signal 207;213, display data latched by the latch circuit 212; 214, a level shifterfor shifting a logic voltage level to a liquid crystal driving voltagelevel; 215, display data of voltage level shifted by the level shifter214; 216, a reference voltage for a liquid crystal driving voltage; 217,a liquid crystal driving circuit for generating a liquid crystal drivingvoltage on the basis of the reference voltage 216; and 218, a group ofliquid crystal driving signals for driving a liquid crystal panel.

In FIG. 2, twelve bits of display data 202, which are for four pixels (3bits for gray scales×4 pixels), are transferred together from thesystem, so that display data corresponding to 160 pixels (4 pixels×40times) are latched successively by the latch circuit 210 on the basis ofthe latch signal 209 generated by the latch address control circuit 208.The thus latched display data 211 corresponding to 160 pixels arefurther latched simultaneously by the latch circuit 212 on the basis ofthe timing signal 207 synchronized with a gate selection signal of ascanning driver. The voltage levels of the display data 213 are shiftedto liquid crystal driving voltage levels by the level shifter 214, sothat the level shifter 214 outputs display data 215. The liquid crystaldriving circuit 217 selects voltage levels corresponding to the displaydata 215 from eight levels V7 to V0 of the reference voltage 216 andoutputs the selected voltage levels as a group of liquid crystal drivingsignals 218. In this manner, display of eight gray scales correspondingto display data can be achieved by driving a liquid crystal panel on thebasis of eight voltage levels.

FIG. 3 shows the relation between liquid crystal driving voltage anddisplay brightness. In liquid crystal, display brightness variescorrespondingly to a voltage applied to a common electrode. Therefore,display of eight gray scales is achieved by applying eight voltagelevels V7 to V0 to the liquid crystal. Further, when voltages which areequal but different in polarity (positive polarity and negativepolarity) are applied to the common electrode, the brightness does notchange. Generally, in order to prevent the liquid crystal panel fromburning, the voltage to be applied thereto is driven to alternatebetween positive polarity and negative polarity periodically.

FIG. 4 is a configuration diagram of a liquid crystal display devicehaving data drivers in opposite sides of a liquid crystal panel. In FIG.4, the reference numeral 401 designates an power supply circuit forgenerating reference voltages for driving liquid crystal; 402, an ACswitching signal expressing AC switching timing; 403 and 404, referencevoltages obtained by AC switching in different timing; 405, a scanningdriver LSI (hereinafter referred to as “scanning driver”) for drivinggate lines of a liquid crystal panel 411; 406, the gate lines of theliquid crystal panel 411 driven by the scanning driver 405; 407, a datadriver for driving data lines arranged in the upper side of the liquidcrystal panel 411; 408, the data lines driven by the data driver 407;409, a data driver for driving data lines arranged in the lower side ofthe liquid crystal panel 411; 410, the data lines driven by the datadriver 409; and 411, the liquid crystal panel.

FIG. 5 shows the timing of an AC switching signal which serves as areference voltage signal for AC switching outputs in the case where datadrivers are arranged in the upper and lower sides of the liquid crystalpanel as shown in FIG. 4. The power supply circuit 401 generates anupper data driver reference AC voltage 403 and a lower data driverreference AC voltage 404 in synchronism with the AC switching signal402. The upper data driver reference AC voltage 403 and the lower datadriver reference AC voltage 404 are reversed to each other in the timingof polarity (positive polarity and negative polarity). The scanningdriver 405 selects gate lines 406 one line by one line successively andpixels on selected one of the gate lines are driven one pixel by onepixel alternately by the upper and lower data drivers 407 and 409.Accordingly, liquid crystal cells on the gate lines successively drivenby the scanning driver 405 can be driven so that liquid crystal cells oneach of the gate lines alternate their polarity between positive one andnegative one). As a result, the quality of an image on the display isimproved.

FIG. 6 is a configuration diagram of a liquid crystal display devicehaving a data driver in one side of a liquid crystal panel. In FIG. 6,the reference numeral 601 designates an power supply circuit forgenerating a reference voltage for driving liquid crystal; 602, an ACswitching signal expressing AC switching timing; 603, a reference ACvoltage obtained by AC switching; 604, a scanning driver for drivinggate lines of a liquid crystal panel 608; 605, the gate lines of theliquid crystal panel 608 driven by the scanning driver 604; 606, a datadriver for driving data lines arranged in the upper side of the liquidcrystal panel 608; 607, the data lines driven by the data driver 606;and 608, the liquid crystal panel.

FIG. 7 shows the timing of an AC switching signal which serves as areference voltage signal for AC switching an output in the case where adata driver is arranged singly in the upper side of the liquid crystalpanel as shown in FIG. 6. The power supply circuit 601 generates areference AC voltage 603 in synchronism with the AC switching signal602. The scanning driver 604 selects gate lines 605 one by onesuccessively so that selected one of the gate lines is driven by theupper data driver 602. Accordingly, liquid crystal cells on the gatelines successively driven by the scanning driver 604 are driven so thatliquid crystal cells on one and the same gate line have the same(positive or negative) polarity. As a result, the quality of an image onthe display is deteriorated.

FIG. 8 is a view showing another voltage applying method adapted to thecase where the data driver shown in FIG. 6 is used. Although FIG. 7 hasshown the case where the reference voltage 603 is supplied as an ACvoltage, FIG. 8 shows the case where burning of the liquid crystal panelis prevented by changing both the electric potential Vcom of the commonelectrode (common electrode drive) and the reference voltage 603. Alsoin this method, all liquid crystal cells on one and the same gate linehave the same (positive or negative) polarity, so that the quality of animage on the display is deteriorated.

Alternate-column inversion drive of the liquid crystal panel has anadvantage in that display quality is improved with compared with thecase of no use of alternate-column inversion drive, because voltagesapplied to liquid crystal cells are inverted on alternate columns sothat the current flowing in the common electrode at the time of liquidcrystal drive becomes smaller. As for the conventional data driverarrangement, therefore, data drivers are arranged in the upper and lowerportions of the liquid crystal panel. On the other hand, the liquidcrystal display device is on strong demands not only for high qualitydisplay but also for small size and light weight. Arrangement of onedata driver in a single side makes it easy to reduce size and weight.The arrangement of one data driver in a single side of the liquidcrystal panel, however, has a problem that display quality deterioratescompared with the case of alternate-column inversion drive of the liquidcrystal panel.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a liquid crystal driverfor performing alternate-column inversion drive in which liquid crystalcells are driven so as to be inverted on alternate columns in order toobtain high image quality while one data driver is arranged in a singleside of a liquid crystal panel in order to reduce the size and weight ofa liquid crystal display, that is, in order to reduce a liquid crystalpanel driving circuit for the purpose of high-density mounting, and toprovide a liquid crystal display device using the liquid crystal driver.

To achieve the foregoing object, according to an aspect of the presentinvention, a voltage generating means for generating a plurality of grayscale voltages on the basis of reference voltages and an output meansfor selecting one gray scale voltage from the generated gray scalevoltages correspondingly to display data and for outputtingdifferent-polarity liquid crystal supply voltages for one and the samedisplay data in the liquid crystal panel on the basis of the selectedgray scale voltage, an AC switching signal and an inversion AC switchingsignal are provided in a liquid crystal driver.

According to another aspect of the present invention, a level-shiftcircuit for shifting the level of a digital input signal is provided ina scanning driver so that the level of the digital input signal isshifted by the level-shift circuit to a signal level allowed operate inthe inside of the scanning driver.

Alternate-column inversion drive can be achieved by one data driver aslong as the aforementioned voltage generating means and theaforementioned output means are used.

Accordingly, the circuit scale of an electric source circuit forgenerating reference voltages can be reduced.

In addition, because the level-shift circuit provided in the input sideof the scanning driver can shift the level of the digital input signalto a signal level allowed to operate in the inside of the scanningdriver, the circuit scale of the liquid crystal display can he reducedwithout necessity of use of any external level-shift circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a liquid crystal display device asa first embodiment of the present invention;

FIG. 2 is a configuration diagram of a conventional liquid crystaldriver;

FIG. 3 is a graph showing voltage-brightness characteristic of liquidcrystal;

FIG. 4 is a configuration diagram of a conventional liquid crystaldisplay device;

FIG. 5 is a timing chart of liquid crystal reference voltage in theprior art;

FIG. 6 is a configuration diagram of a conventional liquid crystaldisplay device;

FIG. 7 is a timing chart of liquid crystal reference voltage in theprior art;

FIG. 8 is a timing chart of liquid crystal output voltage due to commonelectrode AC drive;

FIG. 9 is a block diagram of a liquid crystal driving circuit in thefirst embodiment;

FIG. 10 is a configuration diagram of a gray scale voltage generatingcircuit in the first embodiment;

FIG. 11 is a configuration diagram of an output circuit in the firstembodiment;

FIG. 12 is a configuration diagram of an output buffer circuit in thefirst embodiment;

FIG. 13 is a timing chart of liquid crystal AC output voltages in thefirst embodiment;

FIG. 14 is a view showing process voltages in the first embodiment;

FIG. 15 is a view showing alternate-column inversion drive in the firstembodiment;

FIG. 16 is a view showing alternate-dot inversion drive in the firstembodiment;

FIG. 17 is a view showing the levels of driver voltages in the firstembodiment;

FIG. 18 is a view showing the levels of driver voltages in the firstembodiment;

FIG. 19 is a configuration diagram of the level-shift circuit in thefirst embodiment;

FIG. 20 is a configuration diagram of the level-shift circuit in thefirst embodiment;

FIG. 21 is a block diagram of a liquid crystal driver according to asecond embodiment of the present invention;

FIG. 22 is a block diagram of the gray scale voltage generating circuitin the second embodiment;

FIG. 23 is a block diagram of the output circuit in the secondembodiment;

FIG. 24 is a block diagram of a liquid crystal display device accordingto a third embodiment of the present invention;

FIG. 25 is a block diagram of the liquid crystal driver circuit in thethird embodiment;

FIG. 26 is a configuration diagram of the voltage generating circuit inthe third embodiment;

FIG. 27 is a timing chart showing the generation of liquid crystalreference voltages in the third embodiment;

FIG. 28 is a configuration diagram of a liquid crystal display deviceaccording to a fourth embodiment of the present invention;

FIG. 29 is a configuration diagram of the voltage generating circuit inthe fourth embodiment;

FIG. 30 is a timing chart showing the generation of liquid crystalreference voltages in the fourth embodiment; FIG. 31 is a configurationdiagram of a voltage generating circuit according to a fifth embodimentof the present invention;

FIG. 32 is a timing chart showing the generation of liquid crystalreference voltages in the fifth embodiment;

FIG. 33 is a configuration diagram of a liquid crystal display deviceaccording to a sixth embodiment of the present invention;

FIG. 34 is a block diagram of the liquid crystal driver circuit in thesixth embodiment;

FIG. 35 is a configuration diagram of the voltage generating circuit inthe sixth embodiment;

FIG. 36 is a timing chart showing the generation of liquid crystalreference voltages in the sixth embodiment;

FIG. 37 is a timing chart showing liquid crystal AC output voltagesaccording to a seventh embodiment of the present invention; and

FIG. 38 is a block diagram of the output circuit in the seventhembodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a block diagram of a liquid crystal display device accordingto the present invention. In FIG. 1, the reference numeral 101designates display data transferred from a system; 102, a group ofcontrol signals; 103, an power supply circuit; 104, a group of referencevoltage signals of 9 voltage levels to be applied to liquid crystal;105, an inversion reference voltage for AC inverting a voltage to beapplied to liquid crystal; 106, an AC switching signal expressing thetiming of AC switching; 107, a selection signal for controllinginversion outputs for each column; and 108, a control signal forperforming output circuit driving control. The reference numerals 109-1to 109-8 designate data drivers for 240 outputs; 110, a timing controlcircuit; 111, a group of timing signals, 112, display data; 113, adisplay timing signal expressing display timing; 114, a buffer circuitwhich receives and buffers the group of reference voltage signals 104and the inversion reference voltage 105; and 115 and 119, a referencevoltage and an inversion reference voltage, respectively, outputted fromthe buffer circuit 114.

The reference numeral 116 designates an EOR circuit for performingcontrol as to whether the AC switching signal 106 is to be inverted ornot to be inverted on the basis of the selection signal 107; 117, an ACswitching signal outputted from the EOR circuit 116; 118, a levelshifter circuit for converting the level of the control signal 108 intoa signal level for a high rate withstand voltage process; 120, a signaloutputted from the level shifter circuit 118 by shifting the level ofthe AC switching signal 106; 121, a signal outputted from the levelshifter circuit 118 by shifting the level of the AC switching signal117; and 122, a signal outputted from the level shifter circuit 118 byshifting the level of the control signal 108. The reference numeral 123designates a latch address control circuit; 124, a group of latchsignals generated by the latch address control circuit 123; 125, a latchcircuit for latching the display data 112 successively; 126, displaydata latched by the latch circuit 125; 127, a latch circuit for latchingthe display data 126 simultaneously in synchronism with the displaytiming signal 113; and 128, display data latched by the latch circuit127.

The reference numeral 129 designates a gray scale voltage generatingcircuit for generating 64 levels of gray scale voltages from 9 levels ofreference voltages 115 and outputting one level of gray scale voltagescorresponding to display data; 130, the gray scale voltages generated bythe gray scale voltage generating circuit 129; and 131, an outputcircuit for outputting voltages obtained by inverting or non-invertingthe gray scale voltages 130 on the basis of the inversion referencevoltage 119 correspondingly to the AC switching signals 120 and 121.Output currents of the output circuit 131 are controlled by the controlsignal 122. The reference numeral 132 designates liquid crystal drivingvoltages. The reference numeral 133 designates a scanning circuit; 134,gate driving signals successively selected by the scanning circuit 133;and 135, a liquid crystal panel of 640 dots×480 lines.

In FIG. 1, eight data drivers are required because the number of outputsfrom each of the data drivers 109-1 to 109-8 is 240 and because theresolution of the liquid crystal panel 135 is 640×RGB×480 pixels. Thetiming control circuit 110 generates control signals inside each datadriver on the basis of 18 bits of display data 101 (3 pixels×6 bits forgray scales) and a group of control signals, such as a horizontalsynchronizing signal, a display data transfer clock signal, etc.,transferred from a system and performs timing control. In the timingcontrol circuit 110, the display data 101 are controlled by the timinginside the data driver so as to be transferred as display data 112 tothe latch circuit 125. The latch address control circuit 123 generates alatch signal 124 synchronized with the display data 112 from the controlsignal group 111 outputted from the timing control circuit 110 on thebasis of the timing inside the data driver, so that the display data 112are latched by the latch circuit 125 successively.

Each of the latch circuits 125 has 240 outputs (6 bits per one output)so that display data corresponding to one horizontal line can be latchedsuccessively in the data drivers 109-1 to 109-8. The display data 126thus latched by the latch circuits 125 correspondingly to one horizontalline are further latched simultaneously by the latch circuits 127 on thebasis of the display timing signal 113 synchronized with the gateselection signal 134 outputted from the scanning circuit 133. Each ofthe latch circuits 127 has 240 outputs (6 bits per one output) so thatdisplay data corresponding to one horizontal line can be latchedsimultaneously in the data drivers 109-1 to 109-8. The display data 128thus latched by the latch circuits 127 are transferred to the gray scalevoltage generating circuits 129. The electric source circuit 103generates 9-level reference signals 104 for generating gray scalevoltages and an inversion reference voltage 105 for AC switching. Eachof the buffer circuits 114 buffers the reference voltages 104 and theinversion reference voltage 105 supplied from the power supply circuit103 and supplies these voltages as reference voltage 115 and inversionreference voltage 119 to the gray scale voltage generating circuits 129and the output circuit.

The gray scale voltage generating circuit 129 generates 64 levels ofgray scale voltages from the reference voltages 115, selects one levelof gray scale voltages corresponding to display data for each output andsends the selected voltage level to the output circuit 131. The ACswitching signal 106 is a signal for designating the timing of ACswitching. The selection signal 107 is a signal for selecting whetherthe timing of AC switching is to be changed or not to be changed forevery output. The AC switching signal 117 is a signal obtained byinverting or non-inverting the AC switching signal 106 correspondinglyto the selection signal 107. The control signal 108 is a signal forperforming driving control of the output circuit 131. The input signallevels of the display data 101, control signal group 102, referencevoltage 104, inversion reference voltage 105, AC switching signal 106,selection signal 107 and control signal 108 are all in a range of from 0V to 5 V. On the other hand, the level of the liquid crystal drivingvoltage requires about 15 V for the purpose of AC drive.

Accordingly, it is necessary to use a high rate withstand voltageprocess (rate voltage: 15 V) as the output circuit for outputting liquidcrystal driving voltages. Therefore, the level shifter 118 shifts thelevels of the AC switching signals 106 and 117 and of the control signal108 to high rate withstand voltage levels to supply these signals to theoutput circuit 131. The output circuit 131 inverts or non-inverts thegray scale voltages 130 on the basis of the inversion reference voltage105 correspondingly to the AC switching signals 120 and 121 tobuffer-output inverted/non-inverted voltages as liquid crystal drivingvoltages 132. The scanning circuit 133 generates a gate selection signal134 for selecting horizontal lines one by one on the liquid crystalpanel 135. Thus, the liquid crystal panel 135 is driven by a liquidcrystal driving voltage 132 supplied in synchronism with the gateselection signal 134 so that display can be performed by liquid crystaldriving voltages corresponding to display data, which are among the 64levels of gray scale voltages of positive polarity or negative polarity.

FIG. 9 is a block diagram showing one of the data drivers depicted inFIG. 1. In FIG. 9, the reference numerals 901-1 to 901-240 designate6-bit latch circuits respectively for latching display data on the basisof the latch signal 124; 902-1 to 902-240, 6-bit latch circuitsrespectively for latching the display data simultaneously on the basisof the display timing signal 113; 903, a gray scale voltage generatingcircuit for generating 64 levels of gray scale voltages from 9 levels ofreference voltages 115; 904, 64-level gray scale voltages generated bythe gray scale voltage generating circuit 903; 905-1 to 905-240,selection circuits each of which selects one voltage level from the 64gray scale voltage levels 904 correspondingly to the display data 128for each output; 906-1 to 906-240, output circuits each of which outputsa voltage obtained by inverting or non-inverting the gray scale voltage130 on the basis of the inversion reference voltage 119 correspondinglyto the AC switching signal 120 or 121 for each output; and 132, theliquid crystal driving voltage.

Display data 101 are latched successively by three pixels by the latchcircuit 125 on the basis of the latch signal 124 generated by the latchaddress control circuit 123. Specifically, the display data 112 arelatched by three pixels (18 bits) successively by the latch circuit 125so that display data 112 are latched by 6-bit latch circuits 901-1,901-2 and 901-3 corresponding to the first group of three pixels,latched by 6-bit latch circuits 901-4, 901-5 and 901-6 corresponding tothe second group of three pixels and finally latched by 6-bit latchcircuits 901-238, 901-239 and 901-240 corresponding to the last group ofthree pixels.

Thus, the eight data drivers latch the display data successively, sothat latching of display data corresponding to one line is completed.The display data 126 thus latched by the latch circuit 125correspondingly to one line are further latched by the latch circuit 127simultaneously on the basis of the display timing signal 113. Thereference voltages 104 are 9-level voltages, which are bufferred by thebuffer circuit 114 and outputted as reference voltages 115. Then, thegray scale voltage generating circuit 903 generates 64 levels of grayscale voltages from the 9 levels of reference voltages 115.

Referring now to FIG. 10, the gray scale voltage generating circuit 903will be described in detail. The gray scale voltage generating circuit903 generates 64 levels of gray scale voltages 904 (from VG63 to VG0) bydividing 8 difference voltages between the 9-level reference voltages115 (from V8 to V0) bufferred by the buffer circuit 114 into 8 parts,respectively, with use of a resistance element. On the other hand, theinversion reference voltage 105 is buffered by the buffer circuit 114and outputted as an inversion reference voltage 119.

Referring back to FIG. 9, the gray scale voltages 904 are supplied tothe gray scale voltage selection circuits 905-1 to 905-240 correspondingto the respective outputs. The gray scale voltage selection circuits905-1 to 905-240 decode display data correspondingly to the display data128 corresponding to the respective outputs, and each of the gray scalevoltage selection circuits 905-1 to 905-240 selects one level from the64 levels of gray scale voltages 904 to output the selected voltage as agray scale voltage 130. That is, 64 levels of gray scale voltages 904 ina voltage level range of from 0 V to 5 V are generated from thereference voltages 104 in a voltage level range of from 0 V to 5 V, sothat gray scale voltages 130 corresponding to display data are selectedfrom the 64 levels of gray scale voltages 904 correspondingly to therespective outputs.

Further, the AC switching signal 106 and the selection signal 107 aresupplied to the EOR circuit 116, in which the AC switching signal 106 isoutputted without inversion when the level of the selection signal 107is “Low” whereas the AC switching signal 106 is outputted with inversionwhen the level of the selection signal 107 is “High”. That is, the ACswitching signal 117 is the same as the AC switching signal 106 when thelevel of the selection signal 107 is “Low” whereas the AC switchingsignal 117 is a signal obtained by inverting the AC switching signal 106when the level of the selection signal 107 is “High”. The control signal108 is a signal for designating control of driving currents of theoutput circuits 906-1 to 906-240. The respective levels of the ACswitching signals 106 and 117 and of the control signal 108 are shiftedby the level shifter circuit 118 in order to adjust the voltage to thesignal level of the output circuit 131 allowed to operate in a liquidcrystal driving voltage level range (of from 5 V to −10 V), so thatthese signals are outputted as AC switching signals 120 and 121 and acontrol signal 122, respectively.

In the output circuit 131, each of the output circuits 906-1 to 906-240corresponding to the respective outputs receives a positive-polaritygray scale voltage 130, an inversion reference voltage 119, AC switchingsignals 120 and 121 and a control signal 122 and inverts or non-invertsthe gray scale voltage 130 on the basis of the inversion referencevoltage 119 correspondingly to the AC switching signal to thereby drivethe liquid crystal panel. Referring now to FIG. 11, the output circuit906-1 will be described in detail. The output circuit 906-1 is composedof an inversion amplification circuit 1101, a selection circuit 1103 andan output buffer circuit 1105. A positive-polarity gray scale voltage130 is inverted with respect to the inversion reference voltage 119 bythe inversion amplification circuit 1101, so that the resulting voltageis outputted as an inversion voltage 1102. This inversion voltage 1102is obtained by inverting the positive-polarity gray scale voltage 130.

Either gray scale voltage 130 or inversion voltage 1102 selected by theselection circuit 1103 correspondingly to the AC switching signal 120 isoutputted as an output voltage 1104 and buffered by the output buffercircuit 1105 to drive the liquid crystal panel 135. Referring to FIG.13, the timing of the AC output voltage will be described in detail. ACswitching signals 120 and 121 correspond alternately to even-numberedand odd-numbered data driver outputs, respectively. Accordingly, in thecase where the level of the selection signal 107 is turned to a “High”level, the AC switching signals 120 and 121 become signals inverted toeach other so that the timing of AC switching of the even-numberedoutputs is different from the timing of AC switching of the odd-numberedoutputs. That is, in this case, the odd-numbered outputs have negativepolarity when the even-numbered outputs have positive polarity whereasthe odd-numbered outputs have positive polarity when the even-numberedoutputs have negative polarity. Further, in the case where the level ofthe selection signal 107 is turned to a “Low” level, the AC switchingsignals 120 and 121 have equal polarity so that the timing of ACswitching of the even-numbered outputs becomes equal to the timing of ACswitching of the odd-numbered outputs. That is, in this case, theodd-numbered outputs have positive polarity when the even-numberedoutputs have positive polarity whereas the odd-numbered outputs havepositive negative when the even-numbered outputs have negative polarity.Further, in this case, the positive-polarity gray scale voltage and thenegative-polarity gray scale voltage are reversed so as to be symmetricwith respect to the inversion reference voltage 119 (Vcen).

FIG. 12 is a configuration diagram of the output buffer circuit depictedin FIG. 11. In FIG. 12, the reference numeral 1201 designates adifferential amplification circuit; 1202 and 1203, current amplificationcircuits; and 1204, a selection circuit for making the currentamplification circuit 1203 operative on the basis of the control signal122.

The output buffer circuit 1105 is a voltage follower circuit which makesthe differential amplification circuit 1201 receive the output voltage1104 and makes the current amplification circuits 1202 and 1203 amplifythe current to drive the liquid crystal panel 135. The control signal122 is a signal for controlling the current amplification circuit 1203.The current amplification circuit 1203 is enabled to operate by turningthe level of the control signal 122 to a “High” level so that thecurrent amplification circuit 1203 can cooperate with the currentamplification circuit 1202 to output a large current, whereas thecurrent amplification circuit 1203 is disabled from operating by turningthe level of the control signal 122 to a “Low” level so that the currentamplification circuit 1202 alone can output a small current. In thismanner, electric power consumed by the current amplification circuitscan be saved because current amplification can be performed by using thetwo current amplification circuits 1202 and 1203 when a large outputcurrent is required and because the current amplification circuit 1203can be disabled from operating so that the current amplification circuit1202 alone is used for current amplification when such a large outputcurrent is not required.

Further, circuit portions surrounded by the broken line in the datadriver in FIGS. 1 and 9 represent high rate withstand voltage processes(rate voltage: 15 V) and the others represent low rate withstand voltageprocesses (rate voltage: 5 V). As shown in FIG. 14, the chip area can bereduced by setting the level of the input signal in a range of from 5 Vto GND, which allows the low rate withstand voltage process to operateand by setting the timing control circuit 110, the latch address controlcircuit 123, the latch circuits 125 and 127 and the gray scale voltagegenerating circuit 129 to be low ate withstand voltage processes smallin gate length except setting the output circuit 131 to be a high ratewithstand voltage process large in gate length. In the present state ofthings, the gate length of the low rate withstand voltage process (ratevoltage: about 5 V to about 3 V) which is the latest fine process isfrom about 1.0 μm to about 0.6 μm and the gate length of the high ratewithstand voltage process (rate voltage: about 30 V to about 10 V) isabout 5 μm to about 2 μm.

In the liquid crystal display using data drivers of this embodiment asdescribed above, alternate-column inversion drive can be performed sothat high quality image display can be made even in the case where thedata drivers are arranged in one side of the liquid crystal panel asshown in FIG. 15. Further, alternate-column inversion drive can beperformed by AC switching for each line as shown in FIG. 16, so thathigher quality image display can be made. Further, this embodiment maybe applied to common electrode AC drive as long as the setting of theselection signal 107 can be changed.

Although this embodiment has shown the case where 240-output datadrivers are used as the data drivers, it is to be understood that thepresent invention may be applied also to the case where 192- or160-output data drivers are used as the data drivers and that 192- or160-output data drivers can be provided easily by rearranging the latchaddress control circuits and the latch circuits correspondingly to thenumber of outputs. Although the description of this embodiment has beenmade upon the case where the rate voltage of the low rate withstandvoltage process and the rate voltage of the high rate withstand voltageprocess are 5 V and 15 V, respectively, the same effect as in thisembodiment can be obtained in the case where the rate voltage of the lowrate withstand voltage process and the rate voltage of the high ratewithstand voltage process are, for example, in a range of from 5 V to 3V and in a range of 30 V to 10 V, respectively.

The scanning driver in this embodiment will be described below.

As shown in FIG. 17, the operating voltage level of the data driver andthe operating voltage level of the scanning driver are different fromeach other. Because of the characteristic of TFT of the liquid crystalpanel, it is necessary that the gate selection signal outputted from thescanning driver be a voltage signal having upper and lower limits whichare larger by about 3 V than the respective upper and lower limits ofthe liquid crystal supply voltage outputted from the data driver.Because the digital signal operating level of the scanning driver is 5 Vwhich is a potential difference between VCC and VDD, there arises adifference between the voltage level of the digital input signal of thedata driver and the voltage level of the digital input signal of thescanning driver. In a conventional liquid crystal panel, the level ofthe digital input signal is set as the signal level of the data driverwhile the level of the input signal to the scanning driver which issmall in the number of signal lines is shifted by an external circuit soas to be adjusted before the input signal is inputted to the scanningdriver. This is a main cause of increase in size of peripheral circuitsused for the liquid crystal display.

In this embodiment, a level-shift circuit is provided in the input sideof the scanning driver so that the circuit scale of the peripheralcircuits can be reduced. FIG. 19 shows an example of configuration ofthe level-shift circuit. In FIG. 19, the reference numeral 1901designates a one-signal level-shift circuit using an inversionamplification circuit; 1902, an input signal; 1903, an inversionreference voltage for inversion and amplification; and 1904, a signalobtained by inverting the input signal 1902 and then shifting the levelthereof. This level-shift circuit 1901 can be adapted to various inputvoltage levels as long as the inversion reference signal 1903 is setcorrespondingly to the voltage level of the input signal. Further, FIG.20 shows another example of configuration of the level-shift circuit. InFIG. 20, the reference numeral 2001 designates a level-shift circuit;2002, an input signal; 2003, a signal obtained by non-inverting theinput signal 2002 and then shifting the level thereof; and 2004 and2005, inverter circuits.

The threshold voltage of the inverter circuit 2004 is set to the centerof the input signal level, and the amplitude level thereof is VCC-VSS.The amplitude level of the inverter circuit 2005 is VCC-VSS. In thislevel-shift circuit 2001, inversion/non-inversion level-shifted signalscan be outputted without necessity of the reference voltage as shown inthe level-shift circuit 1901.

Further, as shown in FIG. 18, the level of the input signal may beshifted to the level of VCC-VSS so that circuit operation is performedat the amplitude level of VCC-VSS. Also in this case, the reduction ofthe circuit scale of peripheral circuits can be attained. This can berealized when an inverter circuit having a threshold voltage set to thecenter of the input signal level is provided in the input side of thescanning driver.

As described above, in this embodiment, because a buffer circuit forbuffering 9-level liquid crystal reference voltages 104 is arranged inthe input side of each data driver, the driving current is small so thatthe circuit scale of the electric source circuit 103 can be reduced.

A second embodiment of the present invention in which data drivers forperforming 64-level gray scale display on the basis of 9-level referencevoltages are used will be described below. The gray scale voltagegenerating circuit in this embodiment is different from that in thefirst embodiment, but the other circuits in this embodiment are similarto those in the first embodiment.

FIG. 21 is a detailed block diagram of the data driver 109-1 depicted inFIG. 1.

In FIG. 21, the reference numerals 2101-1 to 2101-240 designateselection circuits each of which selects one level from the referencevoltages 115 correspondingly to display data 128 for each output; 2102-1to 2102-240, output circuits each of which outputs a voltage obtained byinverting or non-inverting the gray scale voltage 130 on the basis ofthe inversion reference voltage 119 correspondingly to the AC switchingsignal 120 or 121 for each output; and 132, liquid crystal drivingvoltages.

The display data 101 are latched by three pixels successively by thelatch circuit 125 on the basis of the latch signal 124 generated by thelatch address control circuit 123. Specifically, the display data 101are latched by three pixels (18 bits) by the latch circuit 125successively in a manner so that display data 112 are latched by 6-bitlatch circuits 901-1, 901-2 and 901-3 corresponding to the first groupof three pixels, next latched by 6-bit latch circuits 901-4, 901-5 and901-6 corresponding to the second group of three pixels and finallylatched by 6-bit latch circuits 901-238, 901-239 and 901-240corresponding to the last group of three pixels.

Thus, the eight data drivers latch the display data successively, sothat latching of display data corresponding one line is completed. Thedisplay data 126 thus successively latched by the latch circuit 125correspondingly to one line are latched simultaneously by the latchcircuit 127 on the basis of the display timing signal 113. The referencevoltages 104 which are 9-level reference voltages are buffered by thebuffer circuit 114 and then outputted as reference voltages 115. On theother hand, the inversion reference voltage 105 is buffered by thebuffer circuit 114 and then outputted as an inversion reference voltage119.

The reference voltages 115 are supplied to the gray scale voltagegenerating circuits 2101-1 to 2101-240 corresponding to respectiveoutputs. The gray scale voltage generating circuits 2101-1 to 2101-240generate gray scale voltages 130 corresponding to display data from thedisplay data 128 and the reference voltages 115 corresponding to therespective outputs.

FIG. 22 is a block diagram of one of gray scale voltage generatingcircuits in a data driver. In FIG. 22, the reference numeral 2201designates a decoder for decoding the display data 128; 2202, a decodedsignal constituted by upper three bits of the display data decoded bythe decoder 2201; 2203, a decoded signal constituted by lower three bitsof the display data decoded by the decoder 2201; 2204, a selectioncircuit for selecting one level from 8 levels of from V8 to V1 among the9-level reference voltages 115 on the basis of he decoded signal 2202;2205, a selection circuit for electing one level from 8 levels of fromV7 to V0 among the 9-level reference voltages 115 on the basis of thedecoded signal 2202; 2206 and 2207, voltages selected by the selectioncircuits 2204 and 2205, respectively; 2208, a voltage dividing circuitfor dividing the potential difference between the selected voltages 2206and 2207 into eight by eight resistance elements; 2209, 8 levels of grayscale voltages obtained by the voltage dividing circuit 2208; and 2210,a selection circuit for selecting one level from the 8 levels of grayscale voltages 2209 on the basis of the decoded signal 2203.

The 6-bit display data 128 which express 64 gray scales are decoded bythe decoder 2201 so that the upper three bits of the display data 128and the lower three bits thereof are independent from each other. Thedecoded signal 2202 of the upper three bits on 8 lines is supplied tothe selection circuits 2204 and 2205, and the decoded signal of thelower three bits on 8 lines is supplied to the selection circuit 2210.The selection circuit 2204 selects one level from 8 levels of from V8 toV1 among the 9-level reference voltages 115 (V8 to V0) correspondinglyto the decoded signal 2202. The selection circuit 2205 selects one levelfrom 8 levels of from V7 to V0 among the 9-level reference voltages 115(V8 to V0) correspondingly to the decoded signal 2202. Assume now thatcombinations of the two voltages which are selected by the selectioncircuits 2204 and 2205, respectively, are V8-V7, V7-V6, V6-V5, V5-V4,V4-V3, V-3-V2, V2-V1, and V1-V0.

The voltage dividing circuit 2208 divides the potential differencebetween the two selected voltages 2206 and 2207 into eight to generate 8levels of gray scale voltages in between the two selected voltages. Theselection circuit 2210 selects one level from the 8 levels of gray scalevoltages 2209 generated by the voltage dividing circuit correspondinglyto the decoded signal 2203 to output the selected level as a gray scalevoltage 130. In this manner, 64 levels of gray scale voltages can begenerated by using eight combinations of the selected voltages 2206 and2207 and division of potential difference in each combination intoeight. That is, 64 levels of gray scale voltages in a range of from 0 Vto 5 V are generated from the reference voltages 104 having voltagelevels of from 0 V to 5 V, so that a gray scale voltage 130corresponding to the display data is selected from the 64 levels of grayscale voltages correspondingly to each output.

FIG. 23 is a block diagram of one of the output circuits 131 in a datadriver. Each of output circuits 2102-1 to 2102-240 corresponding torespective outputs receives a positive-polarity gray scale voltage 130,an inversion reference voltage 119, AC switching signals 120 and 121 anda control signal 122. The gray scale voltage 130 is inverted ornon-inverted on the basis of the inversion reference voltage 119correspondingly to the AC switching signal 120 to thereby drive theliquid crystal panel. The output circuit 2102-1 is composed of anon-inversion amplification circuit 2301, an inversion amplificationcircuit 2302, and a selection circuit 2305. The positive-polarity grayscale voltage 130 is amplified by the non-inversion amplificationcircuit 2301 and outputted as a positive voltage 2303. On the otherhand, the positive-polarity gray scale voltage 130 is inverted on thebasis of the inversion reference voltage 119 by the inversionamplification circuit 2302 and outputted as an inversion voltage 2304.

This inversion voltage 2304 which is a voltage obtained by inverting thepositive-polarity gray scale voltage 130 corresponds to anegative-polarity liquid crystal driving voltage. Either positivevoltage 2303 or inversion voltage 2304 is selected by the selectioncircuit 2305 correspondingly to the AC switching signal 120 andoutputted as an output voltage 132 to drive the liquid crystal panel135.

A third embodiment of the present invention will be described below.This embodiment is different from the first embodiment in the circuitfor inverting the reference voltage.

FIG. 24 is a configuration diagram of the liquid crystal display devicein the third embodiment. In FIG. 24, the reference numeral 2401designates display data transferred from a system; 2402, a group ofcontrol signals; 2403, an AC switching signal expressing the timing ofAC switching; 2404, an power supply circuit or generating referencevoltages which are used for generating liquid crystal driving voltages;and 2405 and 2406, DC reference voltages generated by the electricsource circuit 2404. The reference numerals 2407-1 to 2407-10 designatedata drivers each having 192 outputs. In each of the data drivers, thereference numeral 2408 designates a timing control circuit; 2409, agroup of timing signals; 2410, display data; 2411, a timing signalexpressing display timing; 2412, a latch address control circuit; 2413,a group of latch signals generated by the latch address control circuit2412; 2414, a latch circuit for latching the display data 2410successively; 2415, display data latched by the latch circuit 2414;2416, a latch circuit for latching the display data 2415 simultaneouslyon the basis of the timing signal 2411; and 2417, display data latchedby the latch circuit 2416. The reference numeral 2418 designates avoltage generating circuit for generating AC reference voltages used forAC driving the liquid crystal on the basis of the reference voltages2405 and 2406; and 2419 and 2420, AC reference voltages generated by thevoltage generating circuit. The reference numeral 2421 designates aliquid crystal driving circuit for generating liquid crystal drivingvoltages corresponding to the display data 2417 on the basis of the ACreference voltages 2419 and 2420; and 2422, liquid crystal drivingvoltages generated by the liquid crystal driving circuit 2421. Thereference numeral 2423 designates a scanning circuit; 2424, gate drivingsignals successively selected by the scanning circuit 2423; and 2425, aliquid crystal panel.

Ten data drivers are required because the number of outputs from each ofthe data drivers 2407-1 to 2407-10 is 192 and because the resolution ofthe liquid crystal panel 2425 is 640×RGB×480 pixels. The display data2401 which are 18-bit display data (3 pixels×6 bits for gray scales) aretransferred successively, so that latch signals 2413 synchronized withthe display data 2401 are generated by the latch address controlcircuits 2412 on the basis of the control signal group 2409 to therebylatch the display data 2410 in the latch circuits 2414 successively.Each of the latch circuits 2414 has latch circuits for latching 192pixels (6 bits per one pixel) so that display data corresponding to onehorizontal line can be latched successively in the data drivers 2407-1to 2407-10. The display data 2415 thus latched by the latch circuits2414 correspondingly to one horizontal line are further latchedsimultaneously by the latch circuits 2416 on the basis of the displaytiming signal 2411 synchronized with the gate selection signal 2424outputted from the scanning circuit 2423. The display data 2417 thuslatched are supplied to the liquid crystal driving circuit 2421. Thevoltage generating circuit 2418 generates AC reference voltages 2419 and2420 different in AC switching timing from each other on the basis ofthe reference voltages 2405 and 2406 generated by the power supplycircuit 2404 and the AC switching signal 2403 so as to be supplied tothe liquid crystal driving circuit 2421. In the liquid crystal drivingcircuit 2421, liquid crystal driving voltages 2422 corresponding to thedisplay data 2417 are generated on the basis of the AC referencevoltages 2419 and 2420 to thereby drive the liquid crystal panel 2425.

In FIG. 25, the reference numerals 2501-1 to 2501-192 designate liquidcrystal driving circuits corresponding to respective outputs.

The AC reference voltages 2419 and 2420 are supplied to the liquidcrystal driving circuits 2501-1 to 2501-192 alternately for the 192outputs. Each of the liquid crystal driving circuits 2501-1 to 2501-192generates and outputs 64 levels of liquid crystal driving voltages onthe basis of the display data of 6 bits per one output and 9 levels ofAC reference voltages 2419 or 2420. The 64 levels of liquid crystaldriving voltages can be outputted by selecting 2 levels from the 9levels of AC reference voltages with use of upper 3 bits of the 6-bitdisplay data and then selecting one level from 8 levels of voltagesobtained by dividing the selected two levels of voltages into 8 equalparts with use of lower 3 bits of the display data. In this manner, thedata driver can generate a liquid crystal driving voltage in which ACswitching timing varies correspondingly to each output, so thatalternate-column inversion drive of the liquid crystal panel 2425 can beperformed.

Although this embodiment has shown the case where each of the liquidcrystal driving circuits has a structure in which AC reference voltagesdifferent in AC switching timing are switched over once per one output,the present invention can be applied to the case where AC referencevoltages are switched over once per two outputs or once per a pluralityof outputs.

FIG. 26 is a configuration diagram of one of the voltage generatingcircuits depicted in FIG. 24. In FIG. 26, the reference numerals 2601-0to 2601-8 designate amplification buffer circuits; 2602-0 to 2602-8,differential amplification circuits; and 2603-0 to 2603-8 and 2604-0 to2604-8, selection circuits.

Reference voltages 2405 of 9 levels VLEV0 to VLEV9 from the electricsource circuit 2404 are buffered by the amplification buffer circuits2601-0 to 2601-8 and supplied to the differential amplification circuits2602-0 to 2602-S and the selection circuits 2603-0 to 2603-8 and 2604-0to 2604-8, respectively. In the differential amplification circuits2602-0 to 2602-8, the reference voltages (VLEV0 to VLEV8) 2405 areinverted and outputted on the basis of the reference voltage (VCEN)2406. The selection circuits 2603-0 to 2603-8 and 2604-0 to 2604-8receive the outputs of the amplification buffer circuits 2601-0 to2601-8 and the outputs of the differential amplification circuits 2602-0to 2602-8, respectively, and select these outputs on the basis of the ACswitching signal 2403. Because inverted AC switching signals areinputted to the selection circuits 2604-0 to 2604-8, the polarity ofvoltages selected by the selection circuits 2603-0 to 2603-8 and thepolarity of voltages selected by the selection circuits 2604-0 to 2604-8are reversed to each other.

This timing is shown in FIG. 27. When the level of the AC switchingsignal (M) 2403 is high, AC reference voltages (V1RV0 to V1RV8) 2419selected by the selection circuits 2603-0 to 2603-8 are outputted asvalues VLEV0INV–VLEV8INV, respectively, and AC reference voltages (V2RV0to V2RV8) 2420 selected by the selection circuits 2604-0 to 2604-8 areoutputted as values VLEV0–VLEV8, respectively. When the level of the ACswitching signal (M) 2403 is contrariwise low, AC reference voltages(V1RV0 to V1RV8) 2419 selected by the selection circuits 2603-0 to2603-8 are outputted as values VLEV0–VLEV8, respectively, and ACreference voltages (V2RV0 to V2RV8) 2420 selected by the selectioncircuits 2604-0 to 2604-8 are outputted as values VLEV0INV–VLEV8INV,respectively. In this manner, AC reference voltages 2419 and 2420different in AC switching timing from each other are generated.

A fourth embodiment of the present invention will be described below.This embodiment is similar to the third embodiment except that voltagegenerating circuits used in this embodiment are assembled so as to bedifferent from those in the third embodiment so that this embodiment canbe adapted to common electrode AC drive of the liquid crystal panel.FIG. 28 is a block diagram showing the liquid crystal display deviceaccording to the present invention.

In FIG. 28, the reference numeral 2801 designates control circuits forcontrolling the timing of AC reference voltages; 2802, data drivers; and2803, voltage generating circuits for generating AC reference voltageswhich are used for AC driving the liquid crystal on the basis of thereference voltages 2405 and 2406.

Ten data drivers are required because the number of outputs from each ofthe data drivers 2802-1 to 2802-10 is 192 and because the resolution ofthe liquid crystal panel 2425 is 640×RGB×480 pixels. The display data2401 which are 18-bit display data (3 pixels×6 bits for gray scales) aretransferred successively, so that latch signals 2413 synchronized withthe display data 2401 are generated by the latch address controlcircuits 2412 on the basis of the control signal group 2409 to therebylatch the display data 2410 in the latch circuits 2414 successively.Each of the latch circuits 2414 has latch circuits for latching 192pixels (6 bits per one pixel) so that display data corresponding to onehorizontal line can be latched successively in the data drivers 2802-1to 2802-10. The display data 2415 thus latched by the latch circuits2414 correspondingly to one horizontal line are further latchedsimultaneously by the latch circuits 2416 on the basis of the timingsignal 2411 synchronized with the gate selection signal 2424 outputtedfrom the scanning circuit 2423. The display data 2417 thus latched aresupplied to the liquid crystal driving circuits 2421. The voltagegenerating circuits 2803 generate AC reference voltages 2419 and 2420 onthe basis of the reference voltages 2405 and 2406 generated by theelectric source circuit 2404, the AC switching signal 2403 and thecontrol signal 2801 so as to be supplied to the liquid crystal drivingcircuits 2421. In the liquid crystal driving circuits 2421, liquidcrystal driving voltages 2422 corresponding to the display data 2417 aregenerated on the basis of the AC reference voltages 2419 and 2420 tothereby drive the liquid crystal panel 2425.

FIG. 29 is a block diagram of one of the voltage generating circuits inthe fourth embodiment. In FIG. 29, the reference numeral 2901 designatesa circuit for switching the AC switching timing.

Reference voltages 2405 of 9 levels VLEV0 to VLEV8 from the electricsource circuit 2404 are buffered by the amplification buffer circuits2601-0 to 2601-8 and supplied to the differential amplification circuits2602-0 to 2602-8 and the selection circuits 2603-0 to 2603-8 and 2604-0to 2604-8, respectively. In the differential amplification circuits2602-0 to 2602-8, the voltages (VLEV0 to VLEV8) are inverted withrespect to the reference voltage (VCEN) 2406.

FIG. 30 is a timing chart showing the generation of liquid crystalreference voltages in this case. As is obvious from FIG. 30, thevoltages VLEV0 to VLEV8 are turned to voltages VLEV0INV to VLEV8INVinverted with respect to the reference voltage VCEN. The selectioncircuits 2603-0 to 2603-8 and 2604-0 to 2604-8 receive the outputs ofthe amplification buffer circuits 2601-0 to 2601-8 and the outputs ofthe differential amplification circuits 2602-0 to 2602-8, respectively,and select these outputs on the basis of the AC switching signal 2403.Because the switching circuit 2901 performs exclusive ORing of the ACswitching signal (M) 2403 and the control signal (SVCOM) 2801 andsupplies the result of the exclusive ORing to the selection circuits2604-0 to 2604-8, the polarity of voltages selected by the selectioncircuits 2603-0 to 2603-8 and the polarity of voltages selected by theselection circuits 2604-0 to 2604-8 are reversed to each other when thelevel of the control signal (SVCOM) 2801 is high, and the polarity ofvoltages selected by the selection circuits 2603-0 to 2603-8 and thepolarity of voltages selected by the selection circuits 2604-0 to 2604-8are the same with each other when the level of the control signal(SVCOM) 2801 is low. That is, when the level of the control signal(SVCOM) 2801 is high, the voltage generating timing is the same as thatin the third embodiment.

When the level of the control signal (SVCOM) 2801 is low, as shown inFIG. 30, AC reference voltages (V1RV0 to V1RV8) 2419 selected by theselection circuits 2603-0 to 2603-8 are outputted as values VLEV0INV toVLEV8INV and AC reference voltages (V2RV0 to V2RV8) 2420 selected by theselection circuits 2604-0 to 2604-8 are outputted similarly as valuesVLEV0INV to VLEV8INV as long as the level of the AC switching signal (M)2403 is high, whereas AC reference voltages (V1RV0 to V1RV8) 2419selected by the selection circuits 2603-0 to 2603-8 are outputted asvalues VLEV0 to VLEV8 and AC reference voltages (V2RV0 to V2RV8) 2420selected by the selection circuits 2604-0 to 2604-8 are outputtedsimilarly as values VLEV0 to VLEV8 as long as the level of the ACswitching signal (M) 2403 is low. In the case of common electrode ACdrive, it is necessary to make the AC switching timing of the respectiveoutputs of the data driver equal for AC switching the common electrode(VCOM) as shown in FIG. 30. Accordingly, the timing of AC switching ofthe AC reference voltages 2419 and 2420 can be controlled by switchingthe control signal 2801, so that the present invention can be adapted tocommon electrode drive easily.

A fifth embodiment of the present invention will be described below.This embodiment is similar to the third embodiment except that voltagegenerating circuits used in this embodiment are different from those inthe third embodiment. FIG. 31 is a block diagram of one of the voltagegenerating circuits.

In FIG. 31, the reference numerals 3101-0 to 3101-8 designateamplification buffer circuits; 3102-0 to 3102-8, level-shift circuits;and 3103-0 to 3103-8 and 3104-0 to 3104-8, selection circuits.

Reference voltages 2405 of 9 levels VLEV0 to VLEV8 from the electricsource circuit 2404 are buffered by the amplification buffer circuits3101-0 to 3101-8 and supplied to the level-shift circuits 3102-0 to3102-8 and the selection circuits 3103-0 to 3103-8 and 3104-0 to 3104-8,respectively. In the level-shift circuits 3102-0 to 3102-8, the levelsof the reference voltages (VLEV0 to VLEV8) 2405 are shiftedcorrespondingly to the voltage level of the reference voltage (VSH)2406.

FIG. 32 shows the timing of reference voltages and liquid crystaldriving voltages. The voltages VLEV0 to VLEV8 are turned to voltagesVLEV0SFT to VLEV8SFT having levels shifted by the voltage level VSH,respectively. The selection circuits 3103-0 to 3103-8 and 3104-0 to3104-8 receive the outputs of the amplification buffer circuits 3101-8to 3101-0 and the outputs of the level-shift circuits 3102-0 to 3102-8,respectively, and select these outputs on the basis of the AC switchingsignal 2403. Because inverted AC switching signals are supplied to theselection circuits 3104-0 to 3104-8, the polarity of voltages selectedby the selection circuits 3103-0 to 3103-8 and the polarity of voltagesselected by the selection circuits 3104-0 to 3104-8 are reversed to eachother. When the level of the AC switching signal (M) 2403 is high, ACreference voltages (V1LS0 to V1LS8) 2419 selected by the selectioncircuits 3103-0 to 3103-8 are outputted as values VLEV8SFT to VLEV0SFT,respectively, and AC reference voltages (V2LS0 to V2LS8) 2420 selectedby the selection circuits 3104-0 to 3104-8 are outputted as values VLEV0to VLEV8, respectively.

When the level of the AC switching signal (M) 2403 is contrariwise low,AC reference voltages (V1LS0 to V1LS8) 2419 selected by the selectioncircuits 3103-0 to 3103-8 are outputted as values VLEV0 to VLEV8,respectively, and AC reference voltages (V2LS0 to V2LS8) 2420 selectedby the selection circuits 3104-0 to 3104-8 are outputted as valuesVLEV8SFT to VLEV0SFT, respectively. In this manner, AC referencevoltages 2419 and 2420 different in AC switching timing from each otherare generated.

Next, the operation of the liquid crystal driving circuit 2421 is thesame as in the third embodiment. In the configuration as describedabove, the data drivers can generate liquid crystal driving voltagesdifferent in AC switching timing correspondingly to each output, so thatalternate-column inversion drive of the liquid crystal panel 2425 can beachieved.

A sixth embodiment of the present invention will be described below.

FIG. 33 is a block diagram showing a liquid crystal display device. InFIG. 33, the reference numeral 3301 designates display data transferredfrom a system; 3302, a group of control signals; 3303, an AC switchingsignal expressing the timing of AC switching; 3304, an power supplycircuit for generating reference voltages which are used for generatingliquid crystal driving voltages; and 3305 and 3306, DC referencevoltages generated by the electric source circuit 3330-4. The referencenumerals 3307-1 to 3307-10 designate data drivers each of which has 192outputs. In each of the data drivers, the reference numeral 3308designates a timing control circuit; 3309, a group of timing signals;3310, a data bus for display data and AC switching signal; 3311, atiming signal expressing the display timing; 3312, a latch addresscontrol circuit; 3313, a group of latch signals generated by the latchaddress control circuit 3312; 3314, a latch circuit for latching datathrough the data bus 3310 successively; 3315, a data bus for displaydata latched by the latch circuit 3314 and AC switching signal; 3316, alatch circuit for latching data through the data bus 3315 simultaneouslyon the basis of the timing signal 3311; and 3317, a data bus for displaydata latched by the latch circuit 3316 and AC switching signal.

The reference numeral 3318 designates a voltage generating circuit forgenerating AC reference voltages which are used for AC driving theliquid crystal on the basis of the reference voltages 3305 and 3306; and3319 and 3320, positive-polarity and negative-polarity referencevoltages generated by the voltage generating circuit. The referencenumeral 3321 designates a liquid crystal driving circuit for generatingliquid crystal driving voltages corresponding to the data bus 3317 fordisplay data and AC switching signal on the basis of the referencevoltages 3319 and 3320; and 3322, liquid crystal driving voltagesgenerated by the liquid crystal driving circuit 3321. The referencenumeral 3323 designates a scanning circuit; 3324, gate driving signalssuccessively selected by the scanning circuit 3323; and 3325, a liquidcrystal panel.

Ten data drivers are required because the number of outputs from each ofthe data drivers 3307-1 to 3307-10 is 192 and because the resolution ofthe liquid crystal panel 2425 is 640'RGB×480 pixels. The display data3301 which are 18-bit data (3 pixels×6 bits for gray scales), and the ACswitching signal 3303 composed of 3 bits per 3 pixels, are transferredsuccessively, so that latch signals 3313 synchronized with the displaydata 3301 and the AC switching signal 3303 are generated by the latchaddress control circuits 3312 on the basis of the control signal group3309 to thereby latch the data from the data bus 3310 into the latchcircuits 3314 successively. Each of the latch circuits 3314 has latchcircuits for latching 192 pixels (6 bits for display data and 1 bit forAC switching signal per one pixel) so that display data and AC switchingsignal corresponding to one horizontal line can be latched successivelyin the data drivers 3307-1 to 3307-10.

The display data and AC switching signal latched by the latch circuits3314 correspondingly to one horizontal line are latched simultaneouslythrough the data bus 3315 by the latch circuits 3316 on the basis of thetiming signal 3311 synchronized with the gate selection signal 3324 ofthe scanning circuit 3323. The data bus 3317 thus latched is supplied tothe liquid crystal driving circuits 3321. The voltage generatingcircuits 3318 generate different AC reference voltages 3319 and 3320corresponding to two levels of AC switching on the basis of thereference voltages 3305 and 3306 generated by the electric sourcecircuit 3304 and supply the AC reference voltages 3319 and 3320 to theliquid crystal driving circuits 3321, respectively. The liquid crystaldriving circuits 3321 generate liquid crystal driving voltages 3322corresponding to the display data 3317 on the basis of the AC referencevoltages 3319 and 3320 to thereby drive the liquid crystal panel 3325.

FIG. 34 is a block diagram of one of the liquid crystal drivingcircuits. In FIG. 34, the reference numerals 3401-1 to 3401-192designate liquid crystal driving circuits for respective outputs;3317-1M to 3317-192M, AC switching signals for respective outputs withrespect to the data bus 3317; and 3317-1D to 3317-192D, display data forrespective outputs.

The AC reference voltages 3319 and 3320 are supplied to the liquidcrystal driving circuits 3401-1 to 3401-192 for 192 outputs,respectively. Each of the liquid crystal driving circuits 3401-1 to3401-192 generates 64 levels of liquid crystal driving voltages on thebasis of the data bus 3317 containing 6-bit display data and ACswitching signal per one output and the 9 levels of AC referencevoltages 3319 or 3320. The 64 levels of liquid crystal driving voltagescan be outputted by selecting either AC reference voltage 3319 or ACreference voltage 3320 as an AC switching signal, selecting 2 levelsfrom the 9 levels of AC reference voltages with use of upper 3 bits ofthe 6-bit display data and then selecting one level from 8 levels ofvoltages obtained by dividing the selected two levels of voltages into 8equal parts with use of lower 3 bits of the display data.

FIG. 35 is a block diagram of one of the voltage generating circuits.Reference voltages 3305 of 9 levels VLEV0 to VLEV8 from the electricsource circuit 3304 are buffered by the amplification buffer circuits3501-0 to 3501-8, supplied to the differential amplification circuits3502-0 to 3502-8 and then outputted as reference voltages V1L0 to V1L8,respectively. In the differential amplification circuits 3502-0 to3502-8, the reference voltages (VLEV0 to VLEV8) 3305 are inverted withrespect to the reference voltage (VCEN) 3306 and outputted as referencevoltages V2L0 to V2L8, respectively. The voltages VLEV0 to VLEV8 arebuffered and outputted as reference voltages V1L0 to V1L8 and outputtedas reference voltages V2L0 to V2L8 inverted with respect to VCEN,respectively.

FIG. 36 shows the timing of reference voltage and liquid crystal drivingvoltage. Liquid crystal driving voltages are generated correspondinglyto AC switching signals by inverting the AC switching signals in then-th output terminal Yn and in the (n+1)-th output terminal Yn+1 to eachother. That is, when an output terminal Yn generates a liquid crystaldriving voltage corresponding to the AC reference voltage 3319 (V1L0 toV1L8), the next output terminal Yn+1 generates a liquid crystal drivingvoltage corresponding to the AC reference voltage 3320 (V2L0 to V2L8).When the output terminal Yn generates a liquid crystal driving voltagecorresponding to the AC reference voltage 3320 (V2L0 to V2L8), the nextoutput terminal Yn+1 generates a liquid crystal driving voltagecorresponding to the AC reference voltage 3319 (V1L0 to V1L8).

In the configuration as described above, the data drivers can generateliquid crystal driving voltages different in AC switching timing forrespective outputs, so that alternate-column inversion drive of theliquid crystal panel 3325 can be achieved. Further, the AC switchingtiming can be changed easily once per two outputs, once per a pluralityof outputs, once per one line, or the like, by changing the setting ofthe AC switching signal transferred in synchronism with display data.

Further, as a seventh embodiment of the present invention, there isshown an embodiment of the output circuit for attaining saving ofconsumed electric power and reduction of chip size in the first andsecond embodiments. This embodiment is different from the first andsecond embodiments only in the output circuit. FIG. 37 is a timing chartshowing the timing of output waveforms, and FIG. 38 is a block diagramof the output circuit.

In the first and second embodiments, a combination of a normalamplification circuit and an inversion amplification circuit is requiredfor each output. On the contrary, in this embodiment, a combination of anormal amplification circuit and an inversion amplification circuit isused so as to be common to two outputs, so that the chip size can bereduced. In FIG. 38, the reference numerals 3801-1 to 3801-240 designateselectors which select gray scale voltages correspondingly to adjacentoutputs of gray scale voltages 130-1 to 130-240. The reference numerals3802-1 to 3802-240 designate normal amplification circuits and inversionamplification circuits which pass or invert the gray scale voltagesselected by the corresponding selectors 3801. The reference numerals3803-1 to 3803-240 designate selectors each of which selects one fromoutputs of adjacent amplification circuits 3802. These operations willbe described below in conjunction with output terminals Y1 and Y2. Agray scale voltage 130-1 corresponding to the output terminal Y1 and agray scale voltage 130-2 corresponding to the output terminal Y2 aresupplied to the normal amplification circuit 3802-1 or the inversionamplification circuit 3802-2 through the selectors 3801-1 and 3801-2,respectively. Further, the outputs of the normal amplification circuit3802-1 and the inversion amplification circuit 3802-2 are selected bythe selectors 3803-1 and 3803-2, respectively, and outputted to theoutput terminals Y1, Y2. A selection signal 3805 for the selectors 3801and 3803 is a selection signal switched in synchronism with the ACswitching signal 106. Therefore, when the gray scale voltage 130-1corresponding to the output terminal Y1 is normally supplied to theoutput terminal Y1, the gray scale voltage 130-2 corresponding to theoutput terminal Y2 is inverted with respect to the inversion referencevoltage 119 and then supplied to the output terminal Y2. When the grayscale voltage 130-1 corresponding to the output terminal Y1 iscontrariwise inverted with respect to the inversion reference voltage119 and then supplied to the output terminal Y1, the gray scale voltage130-2 corresponding to the output terminal Y2 is normally supplied tothe output terminal Y2. In this manner, liquid crystal driving voltageswhich are inverted to each other in AC switching timing can be suppliedto adjacent output terminals.

Further, as shown in FIG. 37, before liquid crystal supply voltages areoutputted, an equalizing period in which adjacent output terminals areconnected by the switching circuits 3805-1 to 3805-120 while the outputsare turned into a high impedance state by the switching circuits 3804-1to 3804-240 is provided so that an operation in which precharging to thelevel of 10 V is assisted by positive-polarity and negative-polarityelectric charge on data lines of the liquid crystal panel is carriedout. In this manner, liquid crystal driving power can be reduced byusing electric charge remaining in the liquid crystal panel.

1. A liquid crystal driver comprising: a plurality of output terminalsfor outputting display voltages to be applied to a liquid crystaldisplay device; an input terminal for receiving display datacorresponding to said plurality of output terminals; and output meansfor converting said input display data into said output displayvoltages; wherein said output means selects a display voltage levelcorresponding to one input display data and simultaneously generates twodifferent display voltages from the selected display voltage level sothat either one of said two different display voltages can be selectedas an output display voltage for each of said output terminals.
 2. Aliquid crystal driver according to claim 1, wherein said two differentdisplay voltages are a display voltage higher than a reference voltageand a display voltage lower than the reference voltage.
 3. A liquidcrystal driver according to claim 1, wherein a display voltage to beselected from said two different display voltages is determined on thebasis of a signal received from outside the liquid crystal driver.
 4. Aliquid crystal driver according to claim 1, wherein a display voltage tobe selected from said two different display voltages is determined onthe basis of input information received together with the display data.5. A liquid crystal driver according to claim 2, wherein said twodifferent display voltages are inverted relative to each other so as tobe symmetric relative to each other with respect to said referencevoltage.
 6. A liquid crystal driver according to claim 2, wherein one ofsaid two different display voltages is shifted by an amountcorresponding to said reference voltage compared with another one ofsaid two different display voltages.
 7. A liquid crystal driveraccording to claim 1, wherein said output means includes level-shiftmeans for shifting said output display voltages with respect to saidoutput terminals.
 8. A liquid crystal driver according to claim 1,wherein a signal obtained by periodically switching between said twodifferent display voltages is outputted at each of said outputterminals.
 9. A liquid crystal driver according to claim 2, whereinduring a certain period, a display voltage higher than said referencevoltage and a display voltage lower than said reference voltage arerespectively supplied to two arbitrary adjacent output terminals.
 10. Aliquid crystal driver according to claim 1, wherein the liquid crystaldriver is constituted by one LSI.
 11. A liquid crystal display devicecomprising: a liquid crystal panel including pixel portions which arearranged at positions of intersections of a plurality of data lines anda plurality of scanning lines in the form of a matrix; a scanning driverfor successively supplying voltages to said plurality of scanning lines;and a liquid crystal driver as defined in claim 1 for receiving displaydata and supplying display voltages to said plurality of data lines incorrespondence to said display data.
 12. A liquid crystal display deviceaccording to claim 11, wherein said scanning driver includes alevel-shift circuit for receiving an input signal of a same level as alevel of a signal received by said liquid crystal driver, and shiftingthe level of said input signal to a level allowed to be used in saidscanning driver.
 13. A liquid crystal driver according to claim 1,wherein said output means includes two different-characteristic outputamplification circuits for two adjacent output terminals so that saidtwo different display voltages can be selected and outputted byswitching connections between two gray scale voltage data generated onthe basis of input display data corresponding to said two outputterminals and input terminals of said two output amplification circuits,and connections between output terminals of said two outputamplification circuits and said two output terminals on the basis of anexternal signal.
 14. A liquid crystal driver according to claim 1,wherein said output means includes a combination of a non-inversionoutput amplification circuit and an inversion output amplificationcircuit for two adjacent output terminals so that said two differentdisplay voltages can be alternately outputted by alternately switchingconnections between two gray scale voltage data generated on the basisof input display data corresponding to said two output terminals andinput terminals of said combination of output amplification circuits,and connections between output terminals of said combination of outputamplification circuits and said two output terminals on the basis of anexternal signal.
 15. A liquid crystal driver according to claim 9,wherein said output means includes connection means which connectstogether two adjacent output terminals outputting a display voltagehigher than said reference voltage and a display voltage lower than saidreference voltage so that said two adjacent output terminals areconnected together during a predetermined period before output displayvoltages of the two adjacent output terminals are switched.
 16. A methodof applying display voltages to a liquid crystal display device, themethod comprising the steps of: receiving display data corresponding tooutput terminals which output display voltages; generating gray scaledisplay voltage levels on the basis of reference voltages; selecting oneof the gray scale display voltage levels for each output terminal inaccordance with said display data, the selected gray scale displayvoltage level being a first display voltage for the output terminal;supplying an AC switching signal and an inversion reference voltage,said AC switching signal having a polarity which is periodicallyinverted; inverting said selected gray scale voltage level with respectto said inversion reference voltage to generate an inverted selectedgray scale display voltage level, the inverted selected gray scaledisplay voltage level being a second display voltage for the outputterminal, the second display voltage being different from the firstdisplay voltage, the first display voltage and the second displayvoltage being available simultaneously; selecting one of the firstdisplay voltage and the second display voltage in accordance with the ACswitching signal as an output display voltage for the output terminal;and outputting the output display voltage from the output terminal. 17.A display device comprising: a display panel displaying an image inaccordance with display data and having a plurality of gate lines and aplurality of data lines delimiting a plurality of pixels; a scannerdriver connected to the plurality of gate lines; and a data driverarranged on a single side of the display panel, and having a circuitsimultaneously outputting a plurality of display voltages, a pluralityof selectors, and a plurality of output terminals connected to theplurality of data lines; wherein the plurality of display voltagesinclude a set of positive polarity gray scale voltages and a set ofnegative polarity gray scale voltages, and each of the plurality ofselectors outputs a selected voltage based on the plurality of displayvoltages according to each of the display data, and each of theplurality of the output terminals outputs the selected voltage to eachof the plurality of data lines; and wherein voltages corresponding to anadjacent two of the data lines are of different polarity from eachother, and a polarity of each pixel is inverted at intervals of oneframe time.
 18. A display device according to claim 17, wherein thecircuit generates the plurality of display voltages from a plurality ofreference voltages inputted from the data driver.
 19. A display deviceaccording to claim 17, wherein voltages of pixels in a column directionof said display panel have a same polarity.